Semiconductor device including at least one element

ABSTRACT

A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Utility Patent Application is a continuation application of U.S.Ser. No. 12/048,602 filed Mar. 14, 2008, which is herein incorporated byreference.

BACKGROUND

Embedded wafer level ball grid array (eWLB) technology expands ontypical wafer level packaging technologies by providing the ability foradding additional surface area for interconnecting silicon components ina semiconductor device. Therefore, eWLB technology provides thepossibility of fabricating a semiconductor device by combining bothactive and passive silicon components into a single module. Passivecomponents, however, are typically very small or include geometries(e.g., small surface area with large height) unfavorable to the moldingprocess used to package the semiconductor device. The small componentsmay not adhere to the carrier foil during the molding process due to theforces applied to the small components by the molding process. This maylead the small components to slip and break contact with the carrierfoil.

For these and other reasons, there is a need for the present invention.

SUMMARY

One embodiment provides a semiconductor device. The semiconductor deviceincludes a chip, at least one element electrically coupled to the chip,an adhesive at least partially covering the at least one element, and amold material at least partially covering the chip and the adhesive.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of embodiments and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments andtogether with the description serve to explain principles ofembodiments. Other embodiments and many of the intended advantages ofembodiments will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 illustrates a cross-sectional view of one embodiment of asemiconductor device.

FIG. 2 illustrates a cross-sectional view of another embodiment of asemiconductor device.

FIG. 3 illustrates a cross-sectional view of one embodiment of acarrier.

FIG. 4 illustrates a cross-sectional view of one embodiment of thecarrier and a double-sided adhesive foil.

FIG. 5A illustrates a cross-sectional view of one embodiment of thecarrier, the double-sided adhesive foil, elements, and semiconductorchips.

FIG. 5B illustrates a cross-sectional view of one embodiment of thecarrier, the double-sided adhesive foil, solder elements, andsemiconductor chips.

FIG. 6A illustrates a cross-sectional view of one embodiment of thecarrier, the double-sided adhesive foil, the elements, the semiconductorchips, and an adhesive material.

FIG. 6B illustrates a cross-sectional view of one embodiment of thecarrier, the double-sided adhesive foil, the solder elements, thesemiconductor chips, and an adhesive material.

FIG. 7A illustrates a cross-sectional view of one embodiment of thecarrier, the double-sided adhesive foil, the elements, the semiconductorchips, the adhesive material, and a molding material.

FIG. 7B illustrates a cross-sectional view of one embodiment of thecarrier, the double-sided adhesive foil, the solder elements, thesemiconductor chips, the adhesive material, and a molding material.

FIG. 8A illustrates a cross-sectional view of one embodiment of theelements, the semiconductor chips, the adhesive material, and themolding material after the release of the carrier and the double-sidedadhesive foil.

FIG. 8B illustrates a cross-sectional view of one embodiment of thesolder elements, the semiconductor chips, the adhesive material, and themolding material after release of the carrier and the double-sidedadhesive foil.

FIG. 9A illustrates a cross-sectional view one embodiment of multiplesemiconductor devices prior to singulation.

FIG. 9B illustrates a cross-sectional view of another embodiment ofmultiple semiconductor devices prior to singulation.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purposes ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims.

It is to be understood that the features of the various exemplaryembodiments described herein may be combined with each other, unlessspecifically noted otherwise.

FIG. 1 illustrates a cross-sectional view of one embodiment of asemiconductor device 100. Semiconductor device 100 is fabricated using awafer level packaging process. Semiconductor device 100 includes asemiconductor chip 106, at least one element 108, an adhesive material114, a molding material 110, a redistribution layer 128, and solderballs 112. Adhesive material 114 covers at least a portion of eachelement 108. Molding material 110 encapsulates at least one side of eachsemiconductor chip 106 and at least one side of each element 108 andadhesive material 114. Adhesive material 114 provides stability toelements 108 during the molding process so that elements 108 are notshifted, misplaced, or tilted after the molding process. In oneembodiment, adhesive material 114 includes Durimide, a polyimide, anelastomer, a thermoplastic, an epoxy, or another suitable adhesive.

Semiconductor chip 106 has a first face 105 and an opposing second face107. Semiconductor chip 106 includes contacts 109 with an exposedsurface on the same plane as opposing second face 107. Redistributionlayer 128 also has a first face 124 and an opposing second face 122.First face 124 of redistribution layer 128 is attached along second face107 of chip 106.

In one embodiment, each element 108 is a passive component. In oneembodiment, each element 108 includes a resistor, a capacitor, aninductor, a conductor, a solder element, a conductive sphere, or anothersuitable passive component. In one embodiment, the volume of eachelement 108 is less than the volume of semiconductor chip 106 by atleast a factor of two. In another embodiment, the height of each element108 is greater than the height of chip 106 in the directionperpendicular to redistribution layer 128.

Redistribution layer 128 includes insulating material 116 and conductivetraces 118, which electrically couple semiconductor chip 106 to at leastone element 108. Further, conductive spheres or solder balls 112 can beelectrically coupled to conductive traces 118 at second face 124 ofredistribution layer 128. Conductive traces 118 include Cu or othersuitable conductive material or conductive material stack. Insulatingmaterial 116 includes a polyimide, an epoxy, or another suitabledielectric material.

FIG. 2 illustrates a cross-sectional view of another embodiment of asemiconductor device 120. Semiconductor device 120 is similar tosemiconductor device 100 previously described and illustrated withreference to FIG. 1, except that elements 108 are replaced withconductive spheres or solder elements or balls 138 in semiconductordevice 120. In this embodiment, adhesive material 114 provides stabilityto solder elements 138 during the molding process so that solderelements 138 are not shifted or misplaced after the molding process.Solder elements 138 can be used for 3D-contacts from the front-side tothe back-side of the package.

The following FIGS. 3 through 9B illustrate embodiments of a process forfabricating a semiconductor device. FIGS. 5A, 6A, 7A, 8A, and 9Aillustrate one embodiment for fabricating a semiconductor device, suchas semiconductor device 100 previously described and illustrated withreference to FIG. 1. FIGS. 5B, 6B, 7B, 8B, and 9B illustrate anotherembodiment for fabricating a semiconductor device, such as semiconductordevice 120 previously described and illustrated with reference to FIG.2.

FIG. 3 illustrates a cross-sectional view of one embodiment of a carrier102. Carrier 102 includes a metal, a polymer, silicon, or anothersuitable material.

FIG. 4 illustrates a cross-sectional view of one embodiment of carrier102 and a double-sided adhesive foil 104. A double-sided, releasable,adhesive foil 104 is laminated to carrier 102 or applied to carrier 102using another suitable technique. In other embodiments, other suitableadhesives are used in place of adhesive foil 104.

FIG. 5A illustrates a cross-sectional view of one embodiment of carrier102, double-sided adhesive foil 104, elements 108, and semiconductorchips 106. Each element 108 and each semiconductor chip 106 is placed onadhesive foil 104. In one embodiment, at least two semiconductor chips106 and at least two elements 108 are placed on adhesive foil 104. Inone embodiment, the area of the surface of each element 108 at theinterface to adhesive foil 104 is less than the area of the surface ofsemiconductor chip 106 at the interface to adhesive foil 104.

FIG. 5B illustrates a cross-sectional view of one embodiment of carrier102, double-sided adhesive foil 104, solder elements 138, andsemiconductor chips 106. Each semiconductor chip 106 and each solderelement 138 is placed on adhesive foil 104. In one embodiment, at leasttwo semiconductor chips 106 and at least two solder elements 138 areplaced on adhesive foil 104. Due to the non-planar or spherical form ofsolder elements 138, solder elements 138 have less surface area thansemiconductor chips 106 for attachment to adhesive foil 104.

FIG. 6A illustrates a cross-sectional view of one embodiment of carrier102, double-sided adhesive foil 104, elements 108, semiconductor chips106, and adhesive material 114. In one embodiment, a dispensing needle126 dispenses an adhesive material 114 to adhere each element 108 toadhesive foil 104. Adhesive material 114 includes an epoxy, athermoplastic, a silicone, a polyimide, an elastomer, or anothersuitable material. Adhesive material 114 at least partially covers eachelement 108 and provides improved attachment of elements 108 to adhesivefoil 104 prior to molding. In another embodiment, a printing process, ajetting process, or another suitable process is used to apply adhesivematerial 114 over or at each element 108.

Adhesive material 114 can then be cured by using any suitable form ofenergy (e.g., thermal, chemical) if a curing step is needed for theadhesive material. In one embodiment, semiconductor chip 106 is placedin close proximity to elements 108; thereby adhesive material 114 isalso applied to at least one surface of semiconductor chip 106. Inanother embodiment, adhesive material 114 is applied to at least aportion of adhesive foil 104 before elements 108 are placed on adhesivefoil 104. Elements 108 are then placed into adhesive material 114.

FIG. 6B illustrates a cross-sectional view of one embodiment of carrier102, double-sided adhesive foil 104, solder elements 138, semiconductorchips 106, and adhesive material 114. In one embodiment, a dispensingneedle dispenses an adhesive material 114 to adhere each solder element138 to adhesive foil 104. Adhesive material 114 includes an epoxy oranother suitable material. Adhesive material 114 at least partiallycovers each solder element 138 and provides improved attachment ofsolder elements 138 to adhesive foil 104 prior to molding. In anotherembodiment, a printing process, a jetting process, or another suitableprocess is used to apply adhesive material 114 over or at each solderelement 138.

Adhesive material 114 can then be cured by using any suitable form ofenergy (e.g., thermal, chemical) if a curing step is needed for theadhesive material. In one embodiment, semiconductor chip 106 is placedin close proximity to solder elements 138; thereby adhesive material 114is also applied to at least one surface of semiconductor chip 106. Inanother embodiment, adhesive material 114 is applied to at least aportion of adhesive foil 104 before solder elements 138 are placed onadhesive foil 104. Solder elements 138 are then placed into adhesivematerial 114.

FIG. 7A illustrates a cross-sectional view of one embodiment of carrier102, double-sided adhesive foil 104, elements 108, semiconductor chips106, adhesive material 114, and molding material 110. Adhesive material114, elements 108, and semiconductor chips 106 are at least partiallyencapsulated by molding material 110. In one embodiment, the entireencapsulation process is performed by mold encapsulation. Carrier 102 isplaced in a molding tool. A liquid mold compound having a high viscosityis dispensed in the center of carrier 102 where semiconductor chips 106and elements 108 have been placed. The top of the molding tool isclosed, causing the liquid mold compound to flow from the center to theedges of the molding tool. Flow of the mold compound applies forces onsemiconductor chips 106 and elements 108. Due to adhesive material 114,however, elements 108 do not shift or tilt in response to the forces.

FIG. 7B illustrates a cross-sectional view of one embodiment of carrier102, double-sided adhesive foil 104, solder elements 138, semiconductorchips 106, adhesive material 114, and molding material 110. Adhesivematerial 114, solder elements 138, and semiconductor chips 106 are atleast partially encapsulated by molding material 110 using a similarprocess as described with reference to FIG. 7A. Due to adhesive material114, solder elements 138 do not shift during the molding process.

FIG. 8A illustrates a cross-sectional view of one embodiment of elements108, semiconductor chips 106, adhesive material 114, and moldingmaterial 110 after release of carrier 102 and double-sided adhesive foil104. The release of adhesive foil 104 and carrier 102 is completed afterapplication of molding material 110. One surface of each element 108 andeach semiconductor chip 106 is exposed where adhesive foil 104 waspreviously attached.

FIG. 8B illustrates a cross-sectional view of one embodiment of solderelements 138, semiconductor chips 106, adhesive material 114, andmolding material 110 after release of carrier 102 and double-sidedadhesive foil 104. A surface of each solder element 138 and eachsemiconductor chip 106 is exposed where adhesive foil 104 was previouslyattached.

FIG. 9A illustrates a cross-sectional view of one embodiment of multiplesemiconductor devices prior to singulation. A redistribution layer 128is fabricated. Redistribution layer 128 includes conductive traces 118formed in a conductive layer. Conductive traces 118 on first face 124 ofredistribution layer 128 are electrically coupled to and directlycontact semiconductor chips 106 and/or elements 108. Redistributionlayer 128 also includes insulating material 116 surrounding conductivetraces 118. Conductive spheres or solder balls 112 are electricallycoupled to conductive traces 118 on second face 122 of redistributionlayer 128.

The semiconductor devices are then separated from one another. Thedashed line in FIG. 9A indicates where molding material 110 andredistribution layer 128 are cut to separate the semiconductor devices.Each semiconductor device includes a semiconductor chip 106 and at leastone element 108. The semiconductor devices are separated by sawing,etching, or other suitable method to provide semiconductor devices 100as previously described and illustrated with reference to FIG. 1.

FIG. 9B illustrates a cross-sectional view of another embodiment ofmultiple semiconductor devices prior to singulation. A redistributionlayer 128 and conductive spheres or solder balls 112 are fabricatedusing a similar process as previously described with reference to FIG.9A. The dashed line in FIG. 9B indicates where molding material 110 andredistribution layer 128 are cut to separate the semiconductor devices.Each semiconductor device includes a semiconductor chip 106 and at leastone solder element 138. The semiconductor devices are separated bysawing, etching, or other suitable method to provide semiconductordevices 120 as previously described and illustrated with reference toFIG. 2.

Embodiments provide semiconductor devices using eWLB technology.Elements and/or solder balls are placed on adhesive foil in addition tosemiconductor chips. Adhesive material is deposited over or at theelements and/or solder balls to provide increased stability anddecreased displacement of the elements and/or solder balls during themolding process. After the adhesive material adheres to the elementsand/or solder balls and the adhesive foil, the semiconductor chips,elements and/or solder balls, and adhesive material are encapsulated inmold material.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A semiconductor device comprising: a chip; atleast one element electrically coupled to the chip; an encapsulationmaterial at least partially covering the chip, the encapsulationmaterial directly contacting the chip; and a planar redistribution layerconsisting of one or more conductive traces and an insulating material,one of the conductive traces contacting the chip and the at least oneelement, wherein the at least one element is laterally adjacent to thechip along a direction that is in a plane of an active surface of thechip.
 2. The semiconductor device of claim 1, wherein the at least oneelement comprises one of a resistor, a capacitor, an inductor, aconductor, a solder element, and a conductive sphere.
 3. Thesemiconductor device of claim 1, further comprising: an array of solderelements electrically coupled to the redistribution layer.
 4. Thesemiconductor device of claim 1, further comprising: a redistributionlayer electrically coupling the chip to the at least one element; and anarray of conductive spheres electrically coupled to the redistributionlayer.
 5. The semiconductor device of claim 1, wherein a volume of theat least one element is less than a volume of the chip by at least afactor of two.
 6. The semiconductor device of claim 1, furthercomprising: wherein in a direction perpendicular to the redistributionlayer, a height of the at least one element is greater than a height ofthe chip.
 7. The semiconductor device of claim 6, including aredistribution layer electrically coupling the chip to the at least oneelement.
 8. The semiconductor device of claim 1, wherein one of theconductive traces directly contacts the semiconductor die and thecomponent.
 9. The semiconductor device of claim 1, wherein one ofconductive traces directly connects the semiconductor die and thecomponent.
 10. A wafer level package comprising: a semiconductor die; acomponent; a planar redistribution layer consisting of one or moreconductive traces and an insulating material, one of the conductivetraces contacting the semiconductor die and the component; and amaterial encapsulating at least one side of the semiconductor die and atleast one side of the component, wherein the component is laterallyadjacent to the semiconductor die with respect to the redistributionlayer.
 11. The package of claim 10, wherein the component comprises oneof a resistor, a capacitor, an inductor, a conductor, a solder element,and a conductive sphere.
 12. The package of claim 10, wherein a heightof the component perpendicular to the redistribution layer is greaterthan a width of the component.
 13. The package of claim 10, furthercomprising: a plurality of solder balls electrically coupled to theredistribution layer.
 14. The package of claim 10, further comprising:an adhesive at least partially covering the at least one element; andwherein the encapsulating material covers at least one side of thecomponent and the adhesive material.
 15. The package of claim 10,wherein one of the conductive traces directly contacts the semiconductordie and the component.
 16. A semiconductor device comprising: a chip; atleast one element electrically coupled to the chip; an encapsulant atleast partially covering the chip, the encapsulant directly contactingthe chip; and a planar redistribution layer consisting of conductivetraces and an insulating material, one of the conductive tracescontacting the chip and the at least one element, wherein the at leastone element is laterally adjacent to the chip along a direction that isin a plane of an active surface of the chip.
 17. The semiconductordevice of claim 16, further comprising: an array of solder elementselectrically coupled to the redistribution layer.
 18. The semiconductordevice of claim 16, further comprising: a redistribution layerelectrically coupling the chip to the at least one element; and an arrayof conductive spheres electrically coupled to the redistribution layer.19. The semiconductor device of claim 16, wherein a volume of the atleast one element is less than a volume of the chip by at least a factorof two.
 20. The semiconductor device of claim 16, further comprising:wherein in a direction perpendicular to the redistribution layer, aheight of the at least one element is greater than a height of the chip.